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mt9v125: soc vga digital image sensor features ? mt9v125_ds rev.. w 6/15 en 1 ?semiconductor components industries, llc 2015, 1/4-inch system-on-a-chip (soc) vga ntsc and pal cmos digital image sensor mt9v125 datasheet, rev. w for the latest datasheet revision, please visit www.onsemi.com features ? system-on-a-chip (soc)? completely integrated camera system ? ntsc and pal (true two field) analog composite video output ? low power, interlaced scan cmos image sensor ? itu-r bt.656 parallel output (8-bit, interlaced) ? serial lvds data output ? supports use of external devices for addition of custom overlay graphics ? superior low-light performance ? on-chip image flow processor (ifp) performs sophisticated processing ? color recovery and correction, sharpening, gamma, lens shading correction, and on-the-fly defect correction ? automatic features: auto exposure (ae), auto white balance (awb), auto black reference (abr), auto flicker avoidance, auto color saturation, and auto defect identification and correction ?simple two-wire serial programming interface applications ? automotive ? rear view camera ? side mirror replacement ? blind spot view ? occupant monitoring ? security cameras ? consumer video products data sheet applicable to silicon revision: rev4 notes: 1. measured at 2.8 v, 30 fps, 25c table 1: key performance parameters parameter typical value optical format 1/4-inch (4:3) active imager size 3.63 mm (h) x 2.78 mm (v) 4.57 mm diagonal active pixels 640h x 480v ntsc output 720h x 486v pal output 720h x 576v pixel size 5.6 ? m x 5.6 ? m color filter array rgb paired bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 13.5 mp/s 27 mhz frame rate (vga 640h x 480v) 30 fps at 27 mhz (ntsc) 25 fps at 27 mhz (pal) integration time 16 sC33 ms (ntsc) 16 sC40 ms (pal) adc resolution 10-bit, on-chip responsivity 5 v/lux-sec (550nm) pixel dynamic range 70 db snr max 39 db supply voltage i/o digital 2.5C3.1 v (2.8 v nominal) core digital 2.5C3.1 v (2.8 v nominal) analog 2.5C3.1 v (2.8 v nominal) power consumption 1 operating 320 mw standby 0.56 mw operating temperature C40c to +85c (functional to +105c) package 52-ball ibga
mt9v125_ds rev.. w 6/15 en 2 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documenta- tion, including information on evaluation kits, please visi t our web site at www.onsemi.com. table 2: available part numbers part number product description orderable product attribute description MT9V125IA7XTC-DP color, 0deg cra, ibga package drypack, protective film mt9v125ia7xtc-dr color, 0deg cra, ibga package drypack mt9v125ia7xtc-tp color, 0deg cra, ibga package tape & reel, protective film mt9v125ia7xtc-tr color, 0deg cra, ibga package tape & reel
mt9v125_ds rev.. w 6/15 en 3 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 detailed architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 sensor core modes and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 modes and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 package and die dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 appendix a: serial bus description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 appendix b?sensor core characte ristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
mt9v125_ds rev.. w 6/15 en 4 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor list of figures list of figures figure 1: functional block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: typical usage configuration with overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration without use of overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 52-ball ibga assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: image capture example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: ifp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: awb measurement window (maximum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 12: awb adjusted window size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: mt9v125 in analog composite video mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 14: mt9v125 in sensor stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 15: mt9v125 in overlay output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 16: six pixels in normal and column mirror readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 17: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 18: line_valid formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 19: integration window of each sensor row for ntsc mo de (interlaced readout) . . . . . . . . . . . . . . . . .32 figure 20: single-ended termination?smpte co mpliant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 21: single-ended termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 22: differential connection?smpte-compliant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 23: differential connection?grounded terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 24: differential connection?floating termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 25: lvds serial output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 26: ccir656 8-bit parallel interfac e format for 525/60 (625/50) video systems . . . . . . . . . . . . . . . . . . . .40 figure 27: typical ccir656 vertic al blanking intervals for 525/60 video system. . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 28: typical ccir656 vertic al blanking intervals for 625/50 video system. . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 29: parallel input data timing waveform using din_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 30: parallel input data timing waveform using the extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 31: primary clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 32: typical i/o equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 33: lvds and ntsc blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 34: digital output i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 35: 52-ball ibga package outline dr awing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 36: write timing to r0x009?value 0x 0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 37: read timing from r0x009; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 38: write timing to r0x009?value 0x 0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 39: read timing from r0x009; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 40: serial host clock period and du ty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 41: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 42: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 43: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 44: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 45: acknowledge signal timing after an 8-bit write to the sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 46: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 47: typical signal to noise ratio as a function of exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 48: typical spectral char acteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
mt9v125_ds rev.. w 6/15 en 5 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: readout mode register settings ? d out not qualified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 5: mt9v125 readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 6: readout mode register settings ? d out qualified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7: register address functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 8: blanking minimum values (in sensor stand-alone mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 9: lvds packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 10: serial output data timing values (for extclk = 27 mh z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 11: field, vertical blanking, eav, an d sav states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 12: field, vertical blanking, eav, an d sav states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 13: parallel input data timing values using din_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 14: parallel input data timing values using extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 15: standby effect on the output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 16: signal state during standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 17: output data ordering in dout rgb mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 18: output data ordering in sensor stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 19: data ordering in lvds serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 20: digital output i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 21: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 22: video dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 23: digital i/o parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 24: power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 25: ntsc signal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 26: two-wire interface id address switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 27: mt9v125 rev4 imager sensor core characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
mt9v125_ds rev.. w 6/15 en 6 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor general description general description the on semiconductor mt9v125 is a vga-fo rmat, single-chip camera cmos active- pixel digital image sensor. it captures high-quality color images at vga resolution and outputs ntsc or pal interlaced composite video. this vga cmos image sensor features on semiconductor?s breakthrough technology? a low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low-power, and integration advantages of cmos. the sensor is a complete camera-on-a-chip solution. it incorporates sophisticated camera functions on-chip and is programmab le through a simple two-wire serial inter- face. the mt9v125 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50/60hz fl icker avoidance, lens shading correction, auto white balance (awb), and on-the-fly defect identification and correction. the mt9v125 outputs interlaced-scan images at 30 or 25 fps, supporting both ntsc and pal video formats. the image data can be output on any one of three output ports: ? composite analog video (support for both single-ended and differential-ended) ? low-voltage differential signaling (lvds) ? parallel 8-bit digital functional overview the mt9v125 is a fully-automatic, single-chip camera, requiring only a single power supply, lens, and clock source for basic operat ion. output video is streamed through the chosen output port. the mt9v125 internal registers are configured using a two-wire serial interface. the device can be put into a low-power sleep mode by asserting standby and shutting down the clock. output signals can be tri-stated. both tri-stating output signals and entry into standby mode can be achieved th rough two-wire serial interface register writes. the mt9v125 requires an input clock of 27 mhz to support correct ntsc or pal timing. internal architecture internally, the mt9v125 consists of a sensor core and an image flow processor (ifp). the sensor core captures raw images that are then input into the ifp. the ifp is divided in two sections: the color pipe and the camera controller. the color pipe section processes the incoming stream to create interpolat ed, color-corrected output, and the camera controller section controls the sensor core to maintain the desired exposure and color balance. the ifp scales the image and an integrated video encoder generates either ntsc or pal analog composite output. the mt9v125 suppor ts three different output ports: analog composite video out, lvds serial out, and parallel data out.
mt9v125_ds rev.. w 6/15 en 7 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor functional overview figure 1 shows the major functional blocks of the mt9v125. figure 2 demonstrates an mt9v125 usage scenario. a dsp takes the mt 9v125?s image output, overlays text, and feeds the resulting image back to the mt 9v125 to be output as ntsc or pal. figure 1: functional block diagram figure 2: typical usage configuration with overlay notes: 1. the dsp shown is an external device; it is not part of the mt9v125. sram line buffers image flow processor colorpipe image flow processor camera control image data control bus pixel data sclk s data extclk standby v dd / d gnd v aa / a gnd vaapix lens shading correction color interpolation defect correction color correction gamma correction color conversion + formatting auto exposure auto white balance flicker detect/avoid d out [7:0] pixclk frame_valid line_valid control bus sensor control (gains, shutter, etc.) sensor core 640h x 480v 1/4-inch optical format true interlaced readout auto black compensation programmable analog gain programmable exposure 10-bit adc control bus ntsc and pal encoder and dac lvds formatter and driver lvds_out_pos lvds_out_neg dac_out_pos dac_out_neg d in [7:0] din_clk horizontal interpolator 8 dsp mt9v125 parallel digital signal with overlay (ccir 656) ntsc or pal composite analog output with overlay d in [7:0] d out [7:0] din_clk parallel digital (ccir 656) pixclk 27 mhz oscillator
mt9v125_ds rev.. w 6/15 en 8 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor typical connections typical connections figure 3 shows a detailed mt9v125 device co nfiguration. for low-noise operation, the mt9v125 requires separate an alog and digital power supplies. incoming digital and analog ground conductors can be tied together next to the die. power supply voltages v aa (the primary analog voltage) and vaapix (the main voltage to the pixel array) should be decoupled from ground with an lc filter. the mt9v125 requires a single external voltage supply level. figure 3: typical configuration without use of overlay notes: 1. mt9v125 standby can be connected directly to the customers asic controller or to d gnd , depend- ing on the controllers capability. 2. a 1.5k ? resistor value is recommended, but may be greater for slower two-wire speed (for exam- ple, 100 kb/sec). 3. lvds_enable must be tied high if lvds is to be used. 4. pull down dac_ref with a 2.8k ? resistor for 1.0v peak-to-peak video output. 5. v aa and vaapix must be tied to the same potential for proper operation. 6. low pass filter (3db attenuation at 4.2 mhz). a gnd 0.1f 0.1f v aa d gnd 1f v dd vaapix 1f a gnd 0.1f 1f v dd power v aa power 1.5k 2 1.5k 2 s data sclk reset_bar lvds_enable 3 frame_valid pixclk line_valid d out [7:0] extclk s addr standby 1 1k d gnd a gnd d gnd a gnd v dd v aa vaapix two-wire serial interface master clock standby from controller or digital gnd pedestal ntsc_pal_select horiz_flip dac_neg dac_pos lvds_neg lvds_pos dac_ref 75 2.8k d in [7:0] din_clk d out _lsb[1:0] rsvd 75 75 terminated receiver v dd dac power v dd pll power v dd dac v dd pll 8 2 low pass filter 6 vaapix 5 power
mt9v125_ds rev.. w 6/15 en 9 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor ball assignments ball assignments figure 4 shows the location of the balls and their corresponding signals on the mt9v125. the 12 balls in the middle of the package are unconnected. figure 4: 52-ball ibga assignment table 3: ball descriptions ball assignment name type description f1 extclk input master clock in sensor. g1 reset_bar input active low: asynchronous reset. g3 s addr input two-wire serial interface devi ce id selection 1:0xba, 0:0x90. g4 rsvd input must be attached to d gnd . g4 g2 sclk input two-wire serial interface clock. f2 standby input multifunctional signal to co ntrol device addressing, power-down, and state functions (covering output enable function). g5 horiz_flip input if 0 at reset: default horizontal setting. if 1 at reset: flips the image readout format in the horizontal direction. h3 ntsc_pal_select input if 0 at reset: default ntsc mode. if 1 at reset: default pal mode. h5 pedestal input if 0 at reset: does not add pedestal to composite video output. if 1 at reset: adds pedestal to composite video output. valid for ntsc only, pull low for pal operation. a b c d e f top view (ball down) dac _ref d gnd g h v dd v dd v dd v dd din5 din7 din3 din2 din0 din1 din4 din6 d gnd d gnd d gnd d gnd a gnd s data d out 5 d out 3 d out 1 d out 0 d out 2 d out 4 d out 6 d out 7 v dd dac dac _neg vaapix horiz _flip rsvd s addr s clk reset _bar ntsc _pal_ select l vds_ enable pedestal v aa dac _pos d out _lsb1 d out _lsb0 lvds _pos lvds _neg pixclk v dd pll line_ valid standby ext clk din _clk frame_ valid 1 2 3 4 5 6 7 8
mt9v125_ds rev.. w 6/15 en 10 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor ball assignments notes: 1. all power pins (v dd /v dd dac/v dd pll/v aa /vaapix) must be connected to 2.8v (nominal). power pins cannot be floated. 2. all ground pins (a gnd /d gnd ) must be connected to ground. ground pins cannot be floated. 3. inputs are not tolerant to signal voltages above 3.1v. 4. all unused inputs must be tied to gnd or v dd . 5. v aa and vaapix must be tied to the same potential for proper operation. h4 lvds_enable input active high: enables the lvds output port. must be high if lvds is to be used. a2,b1,b2,c1, c2,d2,e2,d1 d in [7:0] input external data input port selectable at video encoder input. e1 din_clk input d in capture clock. (this clock must be synchronous to extclk.) h2 s data input/output two-wire serial interface data i/o. f7,e7,b3,a3, b4,a4,b5,a5 d out [7:0] output pixel data output d out 7 (most significant bit [msb]), d out 0 (least significant bit [lsb]). data output [9:2] in sensor stand-alone mode c7 d out _lsb0 output sensor stan d-alone mode output 0typically left unconnected for normal soc operation. d7 d out _lsb1 output sensor stan d-alone mode output 1typically left unconnected for normal soc operation. b7 frame_valid output active high: frame_valid (fv); indicates active frame. a6 line_valid output active high: line_valid (lv); indicates active pixel. b6 pixclk output pixel clock output. f8 dac_pos output positive video dac output in differential mode. video dac output in single-ended mode. g7 dac_neg output negative video dac output in differential mode. tie to gnd in single- ended mode h8 dac_ref output external reference resistor for video dac. b8 lvds_pos output lvds positive output. c8 lvds_neg output lvds negative output. f6 a gnd supply analog ground. c3,c6,d8,f3,h7 d gnd supply digital ground. h6 v aa supply analog power: 2.5C3.1v (2.8v nominal). g6 vaapix supply pixel array analog powe r supply: 2.5C3.1v (2.8v nominal). a1,a8,e8,h1 v dd supply digital power: 2.5C3.1v (2.8v nominal). g8 v dd dac supply dac power: 2.5C3.1v (2.8v nominal). a7 v dd pll supply lvds pll power: 2.5C3.1v (2.8v nominal). table 3: ball descriptions (continued) ball assignment name type description
mt9v125_ds rev.. w 6/15 en 11 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview detailed architecture overview sensor core the sensor consists of a pixel array of 695 x 512, an analog readou t chain, a 10-bit adc with programmable gain and black offset, and timing and control as illustrated in figure 5. figure 5: sensor core block diagram pixel array structure the sensor core pixel array is configured as 695 columns by 512 rows, as shown in figure 6. the first 42 columns and the first 13 rows of pixels are optically black, and can be used to monitor the black level. the last four columns and the last row of pixels are also optically black. figure 6: pixel array description communication bus to ifp 10-bit data to ifp sync signals clock control register analog processing active pixel sensor (aps) array timing and control adc 8 + 2 active border rows 1 black row 13 black rows 42 black columns 4 black columns 8 active border rows 4 active border columns 4+1 active border columns active paired bayer pixel array 640 x 480 no horizontal/vertical flip (not to scale) pixel logical address = (694, 511) pixel logical address = (0, 0)
mt9v125_ds rev.. w 6/15 en 12 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview the black row data are used internally for the automatic black level adjustment. however, these black rows can also be read ou t by setting the sensor to raw data output mode. there are 649 columns by 498 rows of opti cally-active pixels that include a pixel boundary around the vga (640 x 480) image to avoid boundary effects during color interpolation and correction. the one additional active column and two a dditional active rows are used to enable horizontally and vertically mirrored re adout to start on the same color pixel. figure 7 illustrates the process of capturing the image. the original scene is flipped and mirrored by the sensor optics. sensor readou t starts at the lower right corner. the image is presented in true orientation by the output display. figure 7: image capture example scene (front view) optics image capture image rendering start readout row by row image sensor (rear view) start rasterization process of i ma g e gatheri n g and i m age displa y display (front view)
mt9v125_ds rev.. w 6/15 en 13 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview the sensor core uses a paired rgb bayer color pattern, as shown in figure 8. row pairs consist of the following: rows 0, 1, rows 2, 3, rows 4, 5, and so on. the even-numbered row pairs (0/1, 4/5, and so on) in the active array contain green and red pixels. the odd- numbered row pairs (2/3, 6/7, and so on ) contain blue and green pixels. the odd- numbered columns contain green and blue pixels; even-numbered columns contain red and green pixels. figure 8: pixel color pattern detail (top right corner) output data format the sensor core image data are read out in an interlaced scan order. progressive readout?which is not supported by the color pipe?is an option, but is only intended for raw data output. valid image data are surrounded by horizontal and vertical blanking, shown in figure 9 on page 14. for ntsc output, the horizontal size is stretc hed from 640 to 720 pixels. the vertical size is 243 pixels per field; 240 imag e pixels and 3 dark pixels that are located at the bottom of the image field. for pal output, the horizontal size is also st retched from 640 to 720 pixels. the vertical size is 288 pixels per field; 24 0 image pixels with 24 dark pi xels at the top of the image and 24 dark pixels at the bottom of the image field. black pixels column readout direction . . . ... row readout direction r r g g r r g g b b g g first active border pixel (42, 15) r r g g r r g g b b g g r r g g r r g g b b g g g g b b g g
mt9v125_ds rev.. w 6/15 en 14 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview figure 9: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 2,0 p 2,1 p 2,2 .....................................p 2,n-1 p 2,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-2,0 p m-2,1 .....................................p m-2,n-1 p m-2,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image odd field horizontal blanking vertical even blanking vertical/horizontal blanking p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n p 3,0 p 3,1 p 3,2 .....................................p 3,n-1 p 3,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m+1,0 p m+1,1 ..................................p m+1,n-1 p m+1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image even field horizontal blanking vertical odd blanking vertical/horizontal blanking
mt9v125_ds rev.. w 6/15 en 15 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview image flow processor (ifp) the mt9v125 ifp consists of a color processi ng pipeline as well as a measurement and control logic block (the camera controller)? see figure 10 on page 16. the stream of raw data from the sensor enters the pipeline and undergoes several transformations. image stream processing starts with conditioning the black level and applying a digital gain. the lens shading block compensates for signal loss caused by the lens. next, the data is interpolated to recover missing color components for each pixel. the resulting interpolated rgb data passes through the current color correction matrix (ccm), gamma, and saturation corrections, and is formatted for final output. the measurement and control logic continuo usly accumulate image brightness and color statistics. based on these measurements, the ifp calculates updated values for exposure time and sensor anal og gains that are sent to the sensor core via the control bus. black level conditioning the sensor core black level calibration works to maintain black pixel values at a constant level, independent of analog gain, reference current, voltage settings, and temperature conditions. if this black level is above zero, it must be reduced before color processing can begin. the black level subtraction block in the ifp re-maps the black level of the sensor to zero prior to lens shading correction. following lens shading correction, the black level addition block provides capability for another black level adjustment. however, for good contrast, this level should be set to zero. digital gain controlled by auto exposure logic, the input digital gain stage amplifies the raw image in low-light conditions (range: x1?x8). test pattern a built-in test pattern generator produces a test image stream that can be multiplexed with the gain stage. the test pattern can be se lected through register settings (see r72:1). there is another set of test patterns at the end of the color pipe that can be selected through register r155:1[5:4]. (see ?register notation? on page 4 of the register reference.)
mt9v125_ds rev.. w 6/15 en 16 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview figure 10: ifp block diagram sensor core colorpipe camera control d out [7:0] pixclk, frame_valid, line_valid raw bayer bypass y gamma correct + color sat ctl + ycrcb rgb horizontal interpolator rgb to ycrcb rgb ryb + color correction + r/b gain for awb interpolate + aperture correct register kernel sram line buffers defect correction flicker detection black level conditioning; digital gain; test pattern at beginning of ifp; lens correction vga pixel sensor including sensor control logic control registers two-wire serial interface control registers ae awb test pattern at end of ifp; camera interface control registers
mt9v125_ds rev.. w 6/15 en 17 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview notes: 1. ntsc encoder/dac not shown lens shading correction (lc) inexpensive lenses tend to attenuate image intensity near the edges of pixel arrays. other factors also cause signal and coloration differences across the image. the net result of all these factors is known as lens shading. lens shading correction (lc) compensates for these differences. typically, the profile of lens shading-induced anomalies across the frame is different for each color component. therefore, lc is inde pendently calibrated for the color channels. interpolation and aperture correction a demosaic engine converts the single-color-per-pixel bayer data from the sensor into rgb (10-bit per color channel). the demosaic algorithm analyzes neighboring pixels to generate a best guess for the missing color components. edge sharpness is preserved as much as possible. aperture correction sharpens the image by an adjustable amount. to avoid amplifying noise, sharpening can be programmed to phase out as light levels drop. defect correction this device supports 2d defect correction. in 2d defect detection and correction, pixels with values different from their neighbors by greater than a defined threshold are considered defects unless near the image boundary. the approach is termed 2d, as pixels on neighboring lines as well as neighboring pixels on the same line are considered in both detection and correction. in figure 10 on page 16, the register kernel gathers same color pixels and send the infor- mation to the 2d defect correction engine. color correction to obtain good color rendition and saturati on, it is necessary to compensate for the differences between the spectral characteristic s of the imager color filter array and the spectral response of the human eye. this compensation, also known as color separation, is achieved through linear transformation of the image with a 3 x 3 element color correc- tion matrix. the optimal values for the colo r correction coefficients depend on the spectra of the incident illumination and can be programmed by the user. color saturation control for noise reduction, both color saturation and sharpness enhancement can be set by the user or adjusted automatically by tracking the magnitude of the gains used by the auto exposure algorithm. automatic white balance (awb) the mt9v125 has a built-in awb algorithm de signed to compensate for the effects of changing scene illumination on the color rend ition quality. this sophisticated algorithm consists of three major submodules: ? a measurement engine (me) performing statistical analysis of the image ? a module selecting the optimal color correction matrix ? a module selecting the analog color channel gains in the sensor core
mt9v125_ds rev.. w 6/15 en 18 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview while the default algorithm settings are adequa te in most situations, the user can repro- gram base color correction matrices and li mit color channel gains. the awb does not attempt to locate the brightest or grayest el ements in the image; it performs in-depth image analysis to differentiate between changes in predominant spectra of illumination and changes in predominant scene colors. fact ory defaults are suit able for most appli- cations; however, a wide range of algorithm parameters can be overwritten by the user through the serial interface. awb measurment window register r0x22d specifies the boundaries of the window used by the wb measurement engine. it describes the size of the window within the image. horizontally, the image value varies from 0 to 9 (64 pixels per unit). vertically, the image value varies from 0 to 6 (32 lines per unit on a per field basis). see figure 12 for an example of adjusting the awb window size (r0x22d = 0x5281). the values in r0x22d are the desired boundaries, in units of square blocks of pixels vertically and horizontally. the size of the bl ock is determined by the resolution of the image seen by the wb measurement engine. for ntsc/pal the size of the block is fixed at 64 x 32 pixels. figure 11: awb measurement window (maximum) figure 12: awb adjusted window size 0 1 2 3 4 5 6 0123 456 789 left to right top to bottom
mt9v125_ds rev.. w 6/15 en 19 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview auto exposure the auto exposure algorithm performs auto matic adjustments to image brightness by controlling exposure time and analog gains in the sensor core, as well as digital gain applied to the image. the algorithm relies on the auto exposure measurement engine that tracks speed and amplit ude changes in the overall luminance of selected windows in the image. backlight compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. other algorithm features include: fast-fluctuating illumination rejection (time -averaging), response-speed control, and controlled sensitivity to small changes. while the default settings are adequate in mo st situations, the user can program target brightness, measurement window, and other pa rameters, as described above. the auto exposure algorithm enables compensation for a broad range of illumination intensities. automatic flicker detection flicker occurs when integration time is not an integer multiple of the period of the light intensity. the automatic flicker detection block does not compensate for the flicker; it reduces flicker occurrence by detecting flicker frequency and adjusting the integration time. for integration times shorter than the light intensity period (10ms for 50hz envi- ronments and 8.33ms for 60hz enviro nments), flicker is unavoidable. gamma correction to achieve more life-like quality in an image, the ifp includes gamma correction and color saturation control. gamma correction operates on the luminance component of the image and enables compensation for nonl inear dependence of the display device output versus the driving signal (for example, monitor brightness versus crt voltage). in addition, gamma correction provides range compression, converting 10-bit lumi- nance input to 8-bit output. pre-gamma imag e processing generate s 10-bit luminance values ranging from 0 to 896. piecewise linear gamma correction utilized in this imager has 10 linear intervals, with end points corresponding to the following input values: xi=0?10 = {0,16,32,64,128,256,384,512,640,768,896} for each input value xi , the user can program the corresponding output value yi. yi values must be monotonically increasing. ntsc and pal encoder formats supported the mt9v125 has an on-chip video encoder to format the data stream for composite video output in the supported ntsc or pal formats. the encoder expects ccir-656 interlaced ntsc or pal data stream input. by default, the input is taken from the on-chip image stream. input can also be taken from the external 8-bit d in [7:0] port for external image processing used with the on-chip video encoder and composite output. mt9v125 readout modes ntsc and pal are two of the target output formats for the mt9v125. table 4 on page 20 identifies registers used to set ntsc or pal modes.
mt9v125_ds rev.. w 6/15 en 20 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview notes: 1. see r the register reference for a description of the register notation. 2. r21:1[0] 3. r19:1[7] 4. r19:1[1:0] 5. r155:1[12] 6. r155:1[8] 7. r155:1[7:6] table 5 identifies the readout format, output format, and output ports supported by the mt9v125. this table gives output formats supported by the mt9v125. the ?devware video output mode? column identifies the name used by the on semiconductor devware demonstration program to execute the readout mode. mt9v125 registers that enable these modes are specified in table 6 on page 21 . table 4: readout mode register settings C d out not qualified when d out is not qualified with fv and lv readout format/ output format/ output port 1 ntsc or pal 2 hold fv high 3 output select mux 4 sensor stand- alone mode 5 enable rgb 6 rgb output format 7 output odd field resolution output even field resolution readout format/ output frame resolution interlaced/ ccir656/ d out [7:0] & lvds 0: ntsc00000720x244720x243720x487 interlaced/ ccir656/ d out [7:0] & lvds 1: pal00000720x288720x288720x576 table 5: mt9v125 readout modes readout formatCoutput format parallel d out composite analog out lvds devware video output mode interlacedCccir656 supported suppo rted supported interlaced/ccir656 interlacedCrgb supported not supported not supported interlaced/rgb interlacedCraw bayer supported not supported not supported interlaced/raw bayer progressiveCraw paired bayer supported not supported not supported progressive/raw paired bayer
mt9v125_ds rev.. w 6/15 en 21 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview table 6: readout mode register settings C d out qualified when d out is qualified with fv and lv notes: 1. see register notation on page 4 of the regist er reference for a description of the register nota- tion. 2. r19:1[7] 3. r21:1[1:0] 4. r19:1[1:0] 5. r155:1[12] 6. r155:1[8] 7. r155:1[7:6] 8. x = dont care readout formats interlaced the default output format, interlaced format, is required for ntsc or pal output. progressive progressive format is used for raw bayer output. output formats itu-r bt.656 and rgb output the mt9v125 can output proce ssed video as a standard itu-r bt.656 (ccir656) stream, an rgb stream, or as unprocessed bayer da ta. the itu-r bt.656 stream contains ycbcr 4:2:2 data with fixed embedded synchronization codes. this output is typically suitable for subsequent display by standard vide o equipment or jpeg/mpeg compression. rgb functionality provides su pport for lcd devices. the mt9v125 can be configured to output 16-bit rgb (565rgb), 15-bit rgb (555rgb), and two types of 12-bit rgb (444rgb). refer to table 17 on page 48 and table 18 on page 48 for details. readout format/ output format/ output port 1 ntsc or pal 2 hold fv high 3 output select mux 4 sensor stand- alone mode 5 enable rgb 6 rgb output format 7 output odd field reso-lution output even field reso-lution output frame reso- lution interlaced/ ccir656/ d out [7:0] & lvds 0: ntsc 1 0 0 0 0 720 x 243 720 x 243 720 x 486 1: pal 1 0 0 0 0 720 x 288 720 x 288 720 x 576 interlaced/ rgb/ d out [7:0] x 8 x 2 0 0 0: rgb 565 1: rgb 555 2: rgb 444x 3: rgb x444 720 x 240 720 x 240 720 x 480 interlaced/ raw bayer/ d out [9:0] x x 2 1 0 0 648 x 248 648 x 248 648 x 596 progressive/ raw paired bayer/ d out [9:0] x x 2 1 0 0 n/a n/a 648 x 488
mt9v125_ds rev.. w 6/15 en 22 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview bayer output unprocessed paired bayer data are generated when bypassing the ifp completely?that is, by simply outputting the sensor-paired bayer stream as usual, using fv, lv, and pixclk to time the data. this mode is called sensor stand-alone mode. output ports composite video output the composite video output dac is external -resistor-programmable and supports both single-ended and diffe rential output. the dac is driven by the on-chip video encoder output. serial data output the processed image data stream can be output to the lvds output port. parallel output parallel output uses either 8-bit or 10-bit output. eight-bit output is used for itu-r bt.656 and rgb output. ten-bit output is used for raw bayer output.
mt9v125_ds rev.. w 6/15 en 23 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview three common data configurations figure 13, figure 14 on page 24, and figure 15 on page 25 demonstrate common config- uration methods for the mt9v125. figure 13 shows the most common usage mode. the processed data from the sensor is output in analog composite video (ntsc or pal) and ccir 656 format through the analog and parallel data output ports, respectively. figure 13: mt9v125 in analog composite video mode tv encoder dac test data internal dac ccir 656 output d out [7:0], fv, lv (without overlay) analog composite video (without overlay) lvds lvds _pos / lvds _neg 0 2 0 1 1 0 r20:1[15:14] = 0 r19:1[2] = 0 async fifo r 155:1[12] = 0 1 0 data flow path sensor ifp encoder preprocessor r19:1[1:0] = 0
mt9v125_ds rev.. w 6/15 en 24 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview figure 14 shows the mt9v125 in sensor stand-alone mode. raw bayer data from the sensor bypasses the ifp to be output directly. only parallel output is available for this mode. figure 14: mt9v125 in sensor stand-alone mode figure 15 on page 25 shows the mt9v125 in overlay output mode that allows the mt9v125 to be configured with an external dsp for text or image overlay. processed sensor data in ccir 656 format is output as parallel data (d out [7-0]). this data is input to a user-supplied dsp that overlays text or graphics on the processed sensor image. dsp outputs ccir 656 image with overlay which is input through the d in port to be multiplexed at the encoder. this encoded data is output as analog composite video (ntsc or pal). tv encoder dac test data internal dac lvds 0 2 0 1 1 0 r19:1[1:0] = 0 r20:1[15:14] = 0 r19:1[2] = 0 async fifo r 155:1[12] = 0 1 0 data flow path sensor ifp encoder preprocessor sensor raw output n/a n/a
mt9v125_ds rev.. w 6/15 en 25 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor detailed architecture overview figure 15: mt9v125 in overlay output mode tv encoder dac test data internal dac lvds 0 2 0 1 1 0 r19:1[1:0] = 0 r20:1[15:14] = 0 r19:1[2] = 0 async fifo r 155:1[12] = 0 1 0 data flow path ifp encoder preprocessor ccir-656 output d out [7:0], lv, fv (without overlay ) analog composite video (with overlay) lvds_pos/ lvds_neg ccir-656 input d in [7:0] (with overlay) dsp (adds overlay separate function off chip) mt9v125 sensor
mt9v125_ds rev.. w 6/15 en 26 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing sensor core modes and timing this section provides an overview of usage modes for the mt9v125 sensor core. an over- view of typical usage modes for the complete mt9v125 is provided in ?modes and timing? on page 33. readout format the sensor core supports two basic readout formats: interlaced and progressive. the interlaced format supports both ntsc and pa l timing. progressive readout is intended for sensor stand-alone mode only (this is due to the paired bayer pattern cfa). window control the window size and position need to be at the default settings for correct ntsc or pal format support. window start the row and column start address of the disp layed image can be set by r1:0 (row start) and r2:0 (column start). window size the default sensor resolution is 640 columns and 480 rows (vga). for ntsc and pal, this is expanded by the horizontal interpol ator module to 720 columns. for proper ntsc or pal operation, use only the default window size. pixel border when r32:0, bits[9:8] are both set, a 4-pixel border will be added around the specified image. when enabled, the row and column widths will be 8 pixels larger than the values programmed in the row and column registers. if the border is enabled but not shown in the image (r32:0[9:8] = 01), the horizontal blanki ng and vertical blanking values will be 8 pixels larger than the values programmed into the blanking registers. for proper ntsc or pal operation, use only default values in the above mentioned registers. the border is read in an interlaced pattern when in interlaced readout mode. each field has its own interlaced border on top and bottom of the active array. sensor core readout modes column mirror image at reset, the horiz_flip input pin is latched into r30:1[1]. this bit is xored with register r21:1[1]. the result determines if horizontal flip is enabled (result = 1) or disabled (result = 0). figure 16 on page 27 il lustrates the readout order of the columns when they are reversed. the starting color is preserved when mirroring the columns. row mirror image by setting r32:0[0] = 1, the readout order of the rows will be reversed, as shown in figure 17 on page 27. the starting color is preserved when mirroring the rows.
mt9v125_ds rev.. w 6/15 en 27 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing figure 16: six pixels in normal and column mirror readout modes figure 17: six rows in normal and row mirror readout modes frame rate control operating mode actual frame rates can be tuned by adjusting various sensor parameters. the sensor registers are in address page 0, some of which are shown in table 7 on page 28. typical settings and parameters for ntsc and pal modes are shown in table 8 on page 23. for a given window size, the blanking regist ers (r0x005, r0x006, r0x011) can be used to set a particular frame rate. g0[9:0] r0[9:0] g1[9:0] r1[9:0] g2[9:0] r2[9:0] g3[9:0] r2[9:0] g2[9:0] r1[9:0] g1[9:0] r0[9:0] line_valid normal readout d out [9:0] reverse readout d out [9:0] row0[9:0] row2[9:0] row4[9:0] row6[9:0] row8[9:0] row10[9:0] row12[9:0] row10[9:0] row8[9:0] row6[9:0] row4[9:0] row2[9:0] frame_valid normal readout d out [9:0] reverse readout d out [9:0]
mt9v125_ds rev.. w 6/15 en 28 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing the sensor timing (table 8 on page 28) is show n in terms of pixel clock and master clock cycles. the required master clock frequency is 27 mhz. the vertical blanking and total frame time equations assume that the number of integration rows (r0x009) is less than the number of active rows, plus blanking rows. if this is not the case, the number of inte- gration rows must be used inst ead to determine the frame time. in the mt9v125, the sensor core adds four bo rder pixels all the way around the image, taking the active image size to 648 x 488. this is achieved through th e default of oversize and show border bits set. ntsc mode has 525 rows per frame; pal mo de has 625 rows per frame as enumerated below (all values in rows): (eq 1) ntsc: (eq 2) pal: (eq 3) blanking calculations when calculating blanking, minimum values for horizontal blanking and vertical blanking must be taken into account. tabl e 8 shows minimum values for each register. this is valid for non ntsc or pal modes only. table 7: register address functions register function r0x004 column width, typically 640 in the mt9v125 r0x003 row width, typica lly 480 in the mt9v125 r0x005 horizontal blanking, default is 210 (units of sensor pixel clocks) r0x006, r0x011 vertical blanking (odd/even), de fault is 14 (odd), 15 (even) (rows including black rows) table 8: blanking minimum values (in sensor stand-alone mode) parameter minimum horizontal blanking 132 (sensor pixel clocks) vertical blanking 6 + # of dark rows oddfieldactive oddfieldvert icalblanking evenfieldactive evenfieldverticalblanking +++ rowsperframe = (42404)14(42404)15 +++++++ 525 = (42404)64(42404)65 +++++++ 625 =
mt9v125_ds rev.. w 6/15 en 29 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing minimum horizontal blanking (in sensor stand-alone mode) the minimum horizontal blanking value is co nstrained by the time used for sampling a row of pixels and the overhead in the row read out. this can be expressed in an equation as: (eq 4) (eq 5) (eq 6) where: (eq 7) (eq 8) with default settings: to get an aggressive minimum value for the horizontal blanking, the larger of r0x079[15:8] and r0x076[15:8] can be substituted for the r0x07e value in the above equation. with default settings, this gives a minimum hblank time of 127. valid data signals options line_valid signal by setting bits[15:14] of r32:0, the lv sign al is programmed for three different output formats. the formats shown below illustrate reading out four rows and two vertical blanking rows (figure 18 on page 30). the default line valid format is shown first; continuous line valid is shown second. in the last format, the lv signal is exclusive ored (xor) between the continuous lv signal and the fv signal. h blank(min) (startup overhead sampling time extra cb time dark col time ? +++ = 31 + done_sample/2 + 16 + (22 read_dark_cols ? ??? = (47 + done_sample/2 + (22 read_dark_cols ??? = done_sample r0x07e (rounded up to nearest even number) = read_dark_cols r0x22:0, (bit[8]) = hblank(min) (47 + 152/2 + 22) 145 pixclk periods = =
mt9v125_ds rev.. w 6/15 en 30 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing figure 18: line_valid formats ntegration time integration time is controlled by r0x009 (shutt er width, in multiples of the row time) and r0x00c (shutter delay, in pixclk_period/2) . r0x00c is used to control sub-row inte- gration times and will only have a visible effect for small values of r0x009. the total inte- gration time, t int, is shown in the equations below (pixclk_period is in terms of master clock periods): (eq 9) where: (eq 10) (eq 11) (eq 12) with default settings for ntsc: (eq 13) with default settings for pal: (eq 14) in this equation, the integration overhead corresponds to the delay between the row reset sequence and the row sample (read) sequence. default frame_valid line_valid continuous frame_valid line_valid frame_valid frame_valid xor line_valid int t r0x009 row time integration overhead ? shutter delay ? ? = row time (r0x004 hblank_reg 8(when border is set)) pixclk_period ? ++ = integration overhead 182 master clock periods = shutter delay r0x00c /2 pixclk_period ? = int t 470 858 2 ? ? ?? 182 ?0 ? 806,388 master clock periods == int t 470 864 2 ? ? ?? 182 ?0 ? 811,978 master clock periods ==
mt9v125_ds rev.. w 6/15 en 31 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing the integration overhead shown is valid only for the default pixclk_period and default sample (r0x07e) and reset (r0x087) values. typically, the value of the shutter width regi ster (r0x009) is limited to the number of rows per frame (which includes vertical blanki ng rows), such that the frame rate is not affected by the integration time. if r0x009 is increased beyond the total number of rows per frame (525 for ntsc, 625 for pal), the sensor will add additional blanking rows as needed and violate the frame time requirement of ntsc and pal. however, the effective value of r0x009 is always limited by the settings in r0x013 and r0x014. a second constraint is that t int must be adjusted to avoid banding in the image caused by light flicker. this means that t int must be a multiple of 1/120 of a second under 60hz flicker, and a multiple of 1/1 00 of a second under 50hz flicker. maximum shutter delay the shutter delay can be used to reduce the integration time. a programmed value of n reduces the integration time by n master clock periods. the maximum shutter delay is set by the row time and the sample time, as shown in the equations below: (eq 15) where: (eq 16) (eq 17) (eq 18) with default settings: (eq 19) (eq 20) if the value in this register exceeds the maximum value given by this equation, the sensor may not generate an image. again, the overhe ad time shown in this equation is only valid for the default pixclk_period, and the default sample (r0x7e:0) and reset (r0x87:0) valuesfigure 19 on page 32, illustrates the integration time for each sensor row versus the shutter width. odd rows are in tegrated first followed by even rows. max shutter delay row time shutter overhead ? = row time (r0x004 hblank_reg) pixclk_period ? + = shutter overhead (ntsc) 356 master clock periods = shutter overhead (pal) 368 master clock periods = ntsc max shutter delay (858 2) 356 ? ? 1360 master clock periods == pal max shutter delay (864 2) 368 ? ? 1360 master clock periods ==
mt9v125_ds rev.. w 6/15 en 32 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor sensor core modes and timing figure 19: integration window of each se nsor row for ntsc mode (interlaced readout) t (seconds) 0/60 1/60 2/60 3/60 4/60 5/60 6/60 . . . . . . 1 30 x 525 time shift per row integration window of each row when shutter width r0x009[15:0] = 525 shutter delay r0x00c[15:0] = 0 t (seconds) 0/60 1/60 3/60 4/60 5/60 6/60 odd rows even rows . . . . . . integration window of each row when shutter width r0x009[15:0] = 1 shutter delay r0x00c[15:0] = 0 note: drawings not to scale 1 30 x 525 row 1 row 496 row 2 row 495 row 3 row 5 odd rows even field vertical blanking 2/60 row1 (first active row) row3 row5 row495 row2 even rows odd field vertical blanking row496
mt9v125_ds rev.. w 6/15 en 33 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing modes and timing this section provides an overview of the typical usage modes and related timing infor- mation for the mt9v125. composite video output the analog composite video output is enabled by default and is the main usage mode for the mt9v125. the external pin ntsc_pal_select can be us ed to configure the device for default ntsc or pal operation. this and other vide o configuration settings are available as register settings accessible through the serial interface. for proper ntsc and pal opera- tion, use only default register values. ntsc both differential and single-e nded connections of the full ntsc format are supported. the differential connection that uses two output lines is used for low noise or long distance applications. the single-ended connection is used for pcb tracks and screened cable where noise is not a concern. the ntsc format has three black lines at the bottom of each image for padding (which most lcds do not display). pal the pal format is supported with 480 active image rows only. black bars are padded on top and bottom of the image for pal format support. the pal format has 24 black lines at the top and bottom of each image for padding. ntsc or pal with external image processing the on-chip video encoder and dac can be used with external data stream input (d in [7:0] port). correct ntsc or pal format ted ccir656 data is required for correct composite video output. this mode can typically be used together with data output on the parallel d out [7:0] port?for example, for external overlay solutions. single-ended and differential composite output the composite output can be operated in a si ngle-ended or differential mode by simply changing the external resistor configuratio n. for single-ended te rmination, two sche- matics are presented. the first is smpte-compliant; the second is a low-cost alternative. for differential mode termination, the first differential schematic; figure 22 on page 36, is smpte-compliant. the other two are lost-cost alternatives. see figure 20 on page 34 through figure 24 on page 37 for termination schematics. note: the differential schematics have not been tested.
mt9v125_ds rev.. w 6/15 en 34 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 20: single-ended terminationsmpte compliant v dd 75 75 chip boundary i = iplus single - ended r = 7 5 r = 7 5 single-ended e . g . pcb track e . g . 75 coax single - end l = 574 nh l = 574 c = 267 c 0 c 1 c = 267 l 0 l 1 l 2 typical values for lc 75 terminat r = 15 c = 740 pf l = 2.7 h r0 r2 r3 c2 l3 nh pf pf l = 1.86 h
mt9v125_ds rev.. w 6/15 en 35 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 21: single-ended termination v dd 75 75 chip boundary i = iplus s single - ended r0 = 7 5 r 1 = 7 5 single-ended e . g . pcb track e . g . 75 coax single - ended l = 680 l = 680 c = 220 c 0 c 1 c = 220 l 0 l 1 l 2 typical values for lc 75 terminated nh nh l = 2.2 h pf pf
mt9v125_ds rev.. w 6/15 en 36 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 22: differential connectionsmpte-compliant l = 383 c2 l1 l2 l3 l = 383 c1 l = 383 nh l = 383 nh l4 l5 l6 r2 r = outyuk outyukp r10 r11 r = 12.5 r = 12.5 butterworth filter @ 12.825 mhz - 3db (differrential) inyukp inyukn c0 c = 965pf l0 l = 2.07 h r3 r = 37.5 r4 r = 5.75 r1 r = 37.5 r0 r = 5.75 io idc 2/37.5 resonant lift (differrential) nh nh l = 1.24 h l = 1.24 h c = 200 pf c = 200 pf
mt9v125_ds rev.. w 6/15 en 37 ?semiconductor components industries, llc,2015 mt9v125: soc vga digital image sensor modes and timing figure 23: differential co nnectiongrounded terminations figure 24: differential co nnectionfloating termination v dd long 75 twisted pair 75 75 chip boundary i = iplus i = iminus differential differential l = 2.2 h l = 680nh l = 680nh c = 220pf c = 220pf c 0 c 1 l 0 l 1 l 2 r 4 r5 c 2 5 v v out amp v ref + - ref fb differential to single - ended conversion typical values for lc 75 terminated receiver r0 = 37.5 r1 = 37.5 r2 = 37.5 r3 = 37.5 r7 = 75 r6 = 75 v dd long 75 twisted pair 75 75 chip boundary i = iplus differential differential c 0 c 1 l 0 l 1 l 2 r4 r5 c 2 5 v v out amp v ref + - ref fb differential to single - ended conversion typical values for lc 75 terminated receiver i = iminus l = 2.2 h l = 680nh l = 680nh c = 220pf c = 220pf r0 = 37.5 r1 = 37.5 r2 = 75 r6 = 75 r7 = 75
mt9v125_ds rev.. w 6/15 en 38 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing serial (lvds) output the serial high-speed output port suppo rts the interlaced ccir-656 data format. the lvds port is disabled by default, but can be enabled by the external pin lvds_en- able. this pin must be asserted for lvds to function. lvds can be disabled through r29:1[13]. lvds is also disabled when standby is asserted. the output lvds format is the standard 12-bit package with 10-bit payload format supported by off-the-shelf deserializers, including national (ds92lv1212a), maxim (max9205), and ti (sn65lv1212). an on-chip x12 pll is included for high-speed lvds clock generation. lvds output clock spee d is 324 mhz for ccir support. table 9 describes the lvds packet format; figure 25 on page 39 shows the lvds data format. table 9: lvds packet format 12-bit packet ccir-656 bit[0] 1 (start bit) bit[1] pixeldata[0] bit[2] pixeldata[1] bit[3] pixeldata[2] bit[4] pixeldata[3] bit[5] pixeldata[4] bit[6] pixeldata[5] bit[7] pixeldata[6] bit[8] pixeldata[7] bit[9] lv bit[10] fv bit[11] 0 (stop bit)
mt9v125_ds rev.. w 6/15 en 39 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 25: lvds serial output data format notes: 1. each lvds packet contains 12 bits. it starts with a 1 (start bit) and ends with a 0 (stop bit). 2. the 8-bit ccir656-compliant video data byte is shifted out with the lsb bit out first, following the start bit. 3. the lv and the fv bits are sent out following the video data byte. 4. a 12x pll generates the internal shift clock from extclk input. the 8-bit d out [7:0] is concatenated with lv and fv outputs and shifted out through the differential lvds_pos/lvds_neg outputs. 5. refer to table 10 for lvds data timing. table 10: serial output data timing values (for extclk = 27 mhz) name min typ max units t dw 2.5 2.7 3.08 ns d1 d0 d3 d2 d5 d4 d7 d6 lv fv internal shift clock lvds serial out start (1) stop (0) ) t dw
mt9v125_ds rev.. w 6/15 en 40 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing parallel output (d out ) interlaced the d out [7:0] port supports outputting the inte rlaced data stream in a variety of formats, as described in more detail in ?itu-r bt.656 and rgb output? on page 21. figure 26 shows the data that is output on the parallel port for ccir656. both ntsc and pal formats are displayed. the blue values in figure 26 represent ntsc (525/60). the red values represent pal (625/50). figure 26: ccir656 8-bit parallel interface format for 525/60 (625/50) video systems figure 27 shows detailed vertical blanking information for ntsc timing. see table 11 on page 42 for data on field, vertic al blanking, eav, and sav states. figure 27: typical ccir656 vertical bl anking intervals for 525/60 video system f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r y c b y c r y c r y f f 4 4 268 280 4 4 1440 1440 1716 1728 eav code blanking sav code co - sited _ co - sited _ start of digital line start of digital active line next line digital video stream blanking field 1 active video blanking field 2 active video line 4 line 266 line 3 field 1 (f = 0) odd field 2 (f = 1) even eav sav line 1 (v = 1) line 20 (v = 0) line 264 (v = 1) line 283 (v = 0) line 525 (v = 0) h = 1 h = 0
mt9v125_ds rev.. w 6/15 en 41 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 28 shows detailed vertical blanking information for pal timing. see table 12 for data on field, vertical blanking, eav, and sav states. figure 28: typical ccir656 vertical bl anking intervals for 625/50 video system table 11: field, vertical blanking, eav, and sav states line number f v h (eav) h (sav) 1C3 1110 4C9 0110 20C263 0 0 1 0 264C265 0 1 1 0 266C282 1 1 1 0 283C525 1 0 1 0 table 12: field, vertical blanking, eav, and sav states line number f v h (eav) h (sav) 1C22 0 1 1 0 23C310 0 0 1 0 311C312 0 1 1 0 313C335 1 1 1 0 336C623 1 0 1 0 624C625 1 1 1 0 blanking field 1 active video blanking field 2 active video field 1 (f = 0) odd field 2 (f = 1) even h = 1 eav h = 0 sav blanking line 1 (v = 1) line 23 (v = 0) line 311 (v = 1) line 336 (v = 0) line 625 (v = 1) line 624 (v = 1)
mt9v125_ds rev.. w 6/15 en 42 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing progressive the d out [7:0] port also supports progressive, raw data output. the on-chip color processor does not support reading out the pi xel array progressivel y, but the raw pixel data can be made available in sensor stand-alone mode. parallel input (d in ) the data-in port allows external ccir656 data to be multiplexed into the ntsc or pal output data. figure 29 shows the timing of the data-in (d in [7:0]) signals. table 13 describes timing values for the parallel input waveform. both mode 0 and mode 1 wave- forms are supported by the mt9v125. figure 29: parallel input data timing waveform using din_clk notes: 1. if r19:1[4] = 1, then din_clk is used to sample data on din bus. 2. setup and hold time is measured with respect to the rising or falling edge of din_clk which can be programmed by r19:1[3]. table 13: parallel input data timing values using din_clk name min typical max function t din_clk 36.975 C C din_clk period t s7CCd in setup time t h8CCd in hold time t din _ clk t s t h d 0 d 1 d 2 d 3 d 4 d 5 d in [7:0] mode 0 t din _ clk t s t h d 0 d 1 d 2 d 3 d 4 d 5 din _ clk mode 1 din _ clk d in [7:0]
mt9v125_ds rev.. w 6/15 en 43 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 30: parallel input data timing waveform using the extclk notes: 1. if r19:1[4] = 0 then the extclk is used to sample the data on din bus. 2. setup and hold time is measured with respect to the rising or fa lling edge of extclk which can be programmed by r19:1[3]. interlaced modes true interlaced by default, the mt9v125 reads out the image array in a true interlaced fashion where each field maps to the odd and even rows respectively. the color pipe is supplied by a regular bayer pattern data stream due to the ?paired bayer? cfa filters used with the pixel array, as described in ?pix el array structure? on page 11. mirroring the mt9v125 supports both horizontal and ve rtical flips, regardless of the output format. horizontal flip, column sequencing re versed, can be enabled by an external pin (horiz_flip) or a register se tting (r21:1[1]). vertical flip can be controlled through a register setting (r32:0[0]). table 14: parallel input data timing values using extclk name min typical max function t extclk 36.975 C C din_clk period t s3CCd in setup time t h14.5CC d in hold time t s t h d 0 d 1 d 2 d 3 d 4 d 5 d in [7:0] mode 0 t s t h d 0 d 1 d 2 d 3 d 4 d 5 mode 1 d in [7:0] extclk extclk t extclk t extclk
mt9v125_ds rev.. w 6/15 en 44 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing reset, clocks, and standby reset power-up reset is asserted/de-asserted with the reset_bar pin, which is active low. in the reset state, all control registers are set to default values. soft reset is asserted/de-asserted by the two- wire serial interface program. in soft-reset mode, the two-wire serial interface and the register bus are still running. all control registers are reset using default values. see r13:0. clocks the mt9v125 has three primary clocks: 1. a master clock coming from the extclk signal. 2. a pixel clock using a clock-gated operation running at half frequency of the master clock in sensor stand-alone mode and the same frequency as extclk in soc mode. 3. din_clk that is associated with the parallel d in port. all device clocks are turned off in power-down mode. when the mt9v125 operates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to conserve power. see r13:0. the sensor core is a master in the system. the sensor core frame rate defines the overall image flow pipeline frame rate. horizontal bl anking and vertical blanking are influenced by the sensor configuration, and are also a fu nction of certain imag e flow pipeline func- tions. the relationship of the primary cl ocks is depicted in figure 31 on page 45. the image flow pipeline typically generates up to 16 bits per pixel?for example, ycbcr or 565rgb?but has only an 8-bit port through which to communicate this pixel data. to generate ntsc or pal format images, the sensor core requires a 27 mhz clock. figure 31: primary clock relationships 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel (typ) 0.5 pixel/clock colorpipe output interface sensor pixel clock sensor master clock extclk sensor core
mt9v125_ds rev.. w 6/15 en 45 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing standby pin standby is a multipurpose signal that contro ls three functions: low-power standby, the two-wire serial interface device address, and output signal state functions. table 15 shows how standby affects the output signal state. two-wire serial interface address is based on the s addr pin xored with the r13:0[10]; the r13:0[10] default is ?0.? see table 26 on page 57 for details. the r13:0[10] is not writ- able when standby is asserted (?1?). hard standby is asserted or de-asserted on standby, as described in ?power-saving modes? on page 47. table 15: standby effect on the output state standby output enable r13:0[6] output disable r13:0[4] standby output state 00 0driven 0 0 1 high-z 10 xdriven x 1 x high-z
mt9v125_ds rev.. w 6/15 en 46 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing power-saving modes the sensor can be put into the low-power stan dby state by either of the following mech- anisms: ? asserting standby (provided that r13:0[7] = 0) ? setting r13:0[3:2] = 01 by performing a regist er write through the serial register inter- face (r13:0[2]: analog standby = 1, r13:0[3]: chip enable = 0) the two methods are equivalent and have the same effect: ? the source of standby is synchronized an d latched. once latched, the full standby sequence is completed even if the source of standby is removed. ? the readout of the current row is completed. ? internal clocks are gated off. ? the analog signal chain and associated cu rrent and voltage sources are placed in a low-power state. the standby state is maintained for as long as the standby source remains asserted. the state of the signal interface while in standby state is shown in table 16 . while in standby, the state of the internal registers is maintained. the sensor continues to respond to accesses through its serial register interface when standby is asserted through a register write, as described above. the serial register interface does not respond when standby mode is entered by asserting the external standby pin. an even lower-power standby state can be achieved by stopping the input clock (extclk) while in standby. if the input clock is stopped, the sensor will not respond to accesses through its two-wire serial register interface. exit from standby must be through the same mechanism as entry to standby. when the standby source is negated: 1. the internal clocks are restarted. 2. the analog circuitry is restored to its normal operating state. 3. the timing and control circuitry perfor ms a restart, equivalent to writing r13:0[1] = 1. after this sequence has completed, normal op eration is resumed. if the input clock has been stopped during standby it must be restarted before leaving standby. floating inputs the following mt9v125 pins cannot be floated: ?d in [7:0] (tie to gnd if not used) ? din_clk (tie to gnd if not used) ? pedestal?valid for ntsc only, this pin should be pulled low for pal ? lvds enable?this pin must always be pulled high if lvds is used ?s data ?this pin is bidirectional and should not be floated table 16: signal state during standby signal state fv 0 lv 0 pixclk 1 d out [7:0], d out _lsb[1:0] 0
mt9v125_ds rev.. w 6/15 en 47 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing output data ordering notes: 1. pixclk is 27 mhz when extclk is 27 mhz. notes: 1. pixclk is 13.5 mh z when extclk is 27 mhz. notes: 1. data output rate is 324 mb/s when extclk is 27 mhz. table 17: output data ordering in d out rgb mode mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 565rgb first r7r6r5r4r3g7g6g5 second g4 g3 g2 b7 b6 b5 b4 b3 555rgb first 0 r7 r6 r5 r4 r3 g7 g6 second g5 g4 g3 b7 b6 b5 b4 b3 444xrgb first r7 r6 r5 r4 g7 g6 g5 g4 second b7 b6 b5 b4 0 0 0 0 x444rgb first 0000r7r6r5r4 second g7 g6 g5 g4 b7 b6 b5 b4 table 18: output data ordering in sensor stand-alone mode mode d7 d6 d5 d4 d3 d2 d1 d0 d out_lsb1 dout_lsb0 10-bit output b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 table 19: data ordering in lvds serial mode mode package[0] package[8:1] package[9] package[10] package[11] default start bit 1 d out [7:0] line_valid frame_valid stop bit 0
mt9v125_ds rev.. w 6/15 en 48 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing i/o circuitry figure 32 and figure 33 on page 50 illustrate ty pical circuitry used for each input, output or i/o pad. figure 32: typical i/o equivalent circuits notes: 1. all i/o circuitry shown above is for reference only. the actual implementation may be different. v dd pad input pad receiver v dd pad output pad tri state driver gnd gnd v dd gnd receiver tri state driver v dd gnd pad v dd gnd gnd i/o pad s data frame_valid line_valid d out _lsb[1:0] d out [7:0] pixclk d in [7:0] din_clk sclk lvds_enable standby pedestal ntsc_pal_select horiz_flip
mt9v125_ds rev.. w 6/15 en 49 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing figure 33: lvds and ntsc blocks notes: 1. all i/o circuitry shown above is for reference only. the actual implementation may be different. v dd_ pll gnd pad v dd_ dac gnd pad pad esd esd out + out lvds output block pad pad esd esd dac_ref esd dac_pos dac_neg ntsc block resistor 2.8k lvds_pos lvds_neg
mt9v125_ds rev.. w 6/15 en 50 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor modes and timing i/o timing digital output by default, the mt9v125 launches pixel data, fv, and lv synchronously with the falling edge of pixclk. the expectation is that the user captures data, fv, and lv using the rising edge of pixclk. the timing diagram is shown in figure 34. as an option, the polarity of the pixclk ca n be inverted from the default. this is achieved by programming r155:1[9] to ?0.? figure 34: digital output i/o timing notes: 1. pixclk may be inverted by programming register r155:1[9] = 0. table 20: digital output i/o timing t a= ambient = 25c; vdd = 2.5C3.1v signal parameter conditions min typ max unit extclk t extclk_high 17 C 20 ns t extclk_low 17 C 20 ns t extclk_period C 37.0 C ns f extclk max +/- 100 ppm 27 mhz pixclk 1 t pixclk_low 14 C 22 ns t pixclk_high 14 C 22 ns t pixclk_period 36.7 37 37.4 ns data[7:0] t extclkr_dout 8 14 18 ns t dout_su 1418.523 ns t dout_ho 1418.523 ns fv/lv t extclkr_fvlv 8 14 18 ns t fvlv_su 14 18.5 23 ns t fvlv_ho 14 18.5 23 ns t dout_su t dout_ho extclk pixclk d out [7:0] frame_valid line_valid t pixclk_low t pixclk_high t extclk_high t fvlv_su t fvlv_ho t extclkr_dout t extclkr_fvlv t extclk_low undefined input output output output t extclk_period t pixclk_period
mt9v125_ds rev.. w 6/15 en 51 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor electrical specifications electrical specifications notes: 1. v dd , v aa , and vaapix must all be at the same potential to avoid excessive current draw. care must be taken to avoid excessive noise injection in th e analog supplies if all three supplies are tied together. table 21: electrical characteristics and operating conditions t a = ambient = 25c; all supplies at 2.8v parameter 1 condition min typ max unit i/o and core digital voltage (v dd ) C 2.5 2.8 3.1 v lvds pll voltage (v dd pll C 2.5 2.8 3.1 v video dac voltage (v dd dac) C 2.5 2.8 3.1 v analog voltage (v aa ) C 2.5 2.8 3.1 v pixel supply voltage (v aapix ) C 2.5 2.8 3.1 v leakage current standby, extclk: high or low 10 ? a imager operating temperature C C40 +85 c functional operating temperature C C40 +105 c storage temperature C C40 +125 c
mt9v125_ds rev.. w 6/15 en 52 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor electrical specifications notes: 1. r dac _ ref =2.8k ? table 22: video dac electrical characteristics t a = ambient = 25c; all supplies at 2.8v parameter condition min typ max unit resolution C 10 C bits dnl single-ended mode C 0.8 1.1 bits inl single-ended mode C 5.7 8.1 bits output local load single-ended mode, output pad (dac_pos) C 75 C ? single-ended mode, unused output (dac_neg) C 0 C ? output voltage single-ended mode, code 000h C 0.02 C v single-ended mode, code 3ffh C 1.42 C v output current single-ended mode, code 000h C 0.6 C ma single-ended mode, code 3ffh C 37.9 C ma dnl differential mode C 0.7 1 bits inl differential mode C 1.4 3 bits output local load differential mode per pad (dac_pos and dac_neg) C 37.5 C ? output voltage differential mode, code 000h, pad dacp C 0.37 C v differential mode, code 000h, pad dacn C 1.07 C v differential mode, code 3ffh, pad dacp C 1.07 C v differential mode, code 3ffh, pad dacn C 0.37 C v output voltage differential mode, code 000h, pad dacp C 0.6 C ma differential mode, code 000h, pad dacn C 37.9 C ma differential mode, code 3ffh, pad dacp C 37.9 C ma differential mode, code 3ffh, pad dacn C 0.6 C ma differential output, mid level differential mode C0.72C v supply current estimate C C 55 ma dac_ref 1 dac reference C 1.15 +/C0.2 v
mt9v125_ds rev.. w 6/15 en 53 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor electrical specifications power consumption notes: 1. 10pf nominal. 2. (ntsc or pal) and lvds should no t be operated at the same time. table 23: digital i/o parameters t a = ambient = 25c; all supplies at 2.8v signal parameter definitions condition min typ max unit all outputs load capacitance 1 C 30 pf output signal slew 2.8v, 30pf load C 0.72 C v/ns 2.8v, 5pf load C 1.25 C v/ns v oh output high voltage 2.5 2.8 3.1 v v ol output low voltage C0.3 C 0.3 v i oh output high current v dd = 2.8v, v oh = 2.4v 16 C 26.5 ma i ol output low current v dd = 2.8v, v ol = 0.4v 15.9 C 21.3 ma all inputs v ih input high voltage v dd = 2.8v 1.48 C v dd +0. 3 v v il input low voltage v dd = 2.8v C C 1.43 v i in input leakage current C2 C 2 ? a signal cap input signal capacitance C 3.5 C pf table 24: power consumption t a = ambient = 25c; all supplies at 2.8v mode sensor (mw) image-flow proc (mw) i/os (mw) 1 dac (mw) lvds (mw) total (mw) active mode 2 60 100 10 150 80 400 standby 0.56
mt9v125_ds rev.. w 6/15 en 54 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor electrical specifications ntsc signal parameters notes: 1. black and white levels are referenced to the blanking level. 2. ntsc convention standardized by the ire (1 ire = 7.14mv). 3. encoder contrast setting r0x011 = r0x001 = 0. 4. dac ref=2.8k ??? load = 37.5 ? table 25: ntsc signal parameters t a = ambient = 25c; all supplies at 2.8v parameter conditions min typ max units notes line frequency 15730 15735 15740 hz field frequency 59.00 59.94 60.00 hz sync rise time 120 164 170 ns sync fall time 120 167 170 ns sync width 4.60 4.74 4.80 ? s sync level 37 39.9 43 ire 2, 4 burst level 37 39.7 43 ire 2, 4 sync to setup (with pedestal off) 9.10 9.40 9.40 ? s sync to burst start 5.00 5.31 5.60 ? s front porch 1.40 1.40 1.60 ? s burst width 8.0 8.5 10.0 cycles black level 6.5 7.5 8.5 ire 1, 2, 4 white level 90 100 110 ire 1, 2, 3, 4
mt9v125_ds rev.. w 6/15 en 55 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor packageanddiedimensions packageanddiedimensions figure 35: 52-ball ibga package outline drawing notes: 1. all dimensions in millimeters. seating plane 9.000 0.075 3.50 3.50 encapsulant: epoxy image sensor die lid material: borosilicate glass 0.40 thickness optical area fuses 0.40 (for reference only) 0.90 5.50 ctr 7.00 5.20 1.845 1.00 typ 9.000 0.075 0.375 0.050 0.525 0.050 0.125 (for reference only) c l c l c l c l 7.00 substrate material: plastic laminate solder ball material: 96.5% sn, 3% ag, 0.5% cu maximum rotation of optical area relative to package edges: 1o 0.10 a a d ball a1 id ball a1 ball a8 52x ?0.55 dimensions apply to solder balls post- reflow. the pre- reflow diameter is ?0.50 on a ?0.40 smd ball pad. 1.00 typ first clear pixel maximum tilt of optical area relative to package edge : 50 microns maximum tilt of optical area relative to top of cover glass: 50 microns d 3.584 ctr 2.688 ctr ?0.15 a b c ?0.15 a b c optical center c b
mt9v125_ds rev.. w 6/15 en 56 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix a: serial bus description appendix a: serial bus description registers are written to and read from the mt9v125 through the two-wire serial inter- face bus. the sensor is a serial interface slave controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred in and out of the mt9v125 through the serial data (s data ) line. the s data and sclk lines are pulled up to v dd off-chip by a 1.5k ? resistor. either the slave or the master device can pull the s data line down?the serial interface protocol dete rmines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? an acknowledge bit ?a no-acknowledge bit ? an 8-bit message ?a stop bit ? the slave device 8-bit address the s addr pin and r13:0[10] are used to select between two different addresses in case of conflict with another device. if s addr xor r13:0[10] is low, the slave address is 0x90; if s addr xor r13:0[10] is high, the slave address is 0xba. see table 26 below. sequence a typical read or write sequence begins with the master sending a start bit. after the start bit, the master sends the 8-bit slave device address. the last bit of the address determines if the request is a read or a write, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its addr ess by sending an acknowledge bit back to the master. if the request was a write, the master transfers the 8-bit register address for where a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data, 8 bits at a time, with the slave sending an ackn owledge bit after each 8 bits. the mt9v125 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are tran sferred, the register address is automatically incremented, so that the next 16 bits are wri tten to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as foll ows. the master sends the write mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read mode slave address. the master clocks out the register data, 8 bits table 26: two-wire interface id address switching s addr r13:0[10] two-wire interface address id 00 0x90 01 0xba 10 0xba 11 0x90
mt9v125_ds rev.. w 6/15 en 57 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix a: serial bus description at a time and sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interface device consists of seven bits of address and one bit of direction. a ?0? in the lsb of the address indicates write mode, and a ?1? indi- cates read mode. the write address of the sensor is 0xba; the read address is 0xbb. this applies only when the s addr is set high. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred eight bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing or the slave when reading) releases the data line, and the receiver signals an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
mt9v125_ds rev.. w 6/15 en 58 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix a: serial bus description two-wire serial interface sample write and read sequences (s addr = 1). 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 36. a start bit sent by the master starts the sequence, foll owed by the write address. the image sensor sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit transfer, the image sensor sends an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 36: write timing to r0x009value 0x0284 16-bit read sequence a typical read sequence is shown in figure 37. the master writes the register address, as in a write sequence. then a start bit and the read address specify that a read is about to occur from the register. the master then clocks out the register data, 8 bits at a time. the master sends an acknowledge bit after each 8- bit transfer. the register address should be incremented after every 16 bits is transferre d. the data transfer is stopped when the master sends a no-acknowledge bit. figure 37: read timing from r0x009; returned value 0x0284 8-bit write sequence to be able to write one byte at a time to th e register, a special register address is added. the 8-bit write is started by writing the upper 8 bits to the desired register, then writing the lower 8 bits to the special register addres s (r0x0f1). the register is not updated until all 16 bits have been written. it is not po ssible to update just half of a register. in figure 38 on page 60, a typical sequence for an 8-bit write is shown. the second byte is written to the special register (r0x0f1). sclk s data 0xba address start sto p ack ack ack ack reg 0x009 0000 0010 1000 0100 sclk s data 0xba address start start stop ack ack ack ack nack reg0x009 0xbb address 0000 0010 1000 0100
mt9v125_ds rev.. w 6/15 en 59 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix a: serial bus description figure 38: write timing to r0x009value 0x0284 8-bit read sequence to read one byte at a time, the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (r0x0f1), the lower 8 bits are accessed (figure 39). the master sets the no-acknowledge bits. figure 39: read timing from r0x009; returned value 0x0284 sclk s data 0xba address start stop ack ack ack ack reg0x009 0xba address start ack ack reg0x0f1 0000 0010 1000 0100 sclk s data 0xba address start start ack ack ack nack reg0x009 0xbb address 0000 0010 sclk s data 0xba address start start stop ack ack ack nack reg0x0f1 0xbb address 1000 0100 ? ? ? ? ? ? continued
mt9v125: soc vga digital image sensor appendix a: serial bus description mt9v125_ds rev.. w 6/15 en 60 ?semiconductor components industries, llc,2015. two-wire serial bus timing the two-wire serial interface operation re quires a certain minimum of master clock cycles between transitions. these are specified below in master clock cycles. figure 40: serial host clock period and duty cycle figure 41: serial host interface start condition timing figure 42: serial host inte rface stop condition timing notes: 1. all timing are in units of master clock cycle. figure 43: serial host interface data timing for write notes: 1. s data is driven by an off-chip transmitter. sclk < 400 khz max sclk 4 s data 4 sclk 5 s data 4 sclk 4 s data 4
mt9v125_ds rev.. w 6/15 en 61 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix a: serial bus description figure 44: serial host interface data timing for read notes: 1. s data is pulled low by the sensor or allowed to be pulled high by a pull-up resistor off-chip. figure 45: acknowledge signal timing after an 8-bit write to the sensor figure 46: acknowledge signal timing after an 8-bit read from the sensor notes: 1. after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sclk 5 s data sclk sensor pulls down s data pin 7 s data 6 sclk sensor tri-states s data pin (turns off pull down) 7 s data 6
mt9v125: soc vga digital image sensor appendix bCsensor core characteristics mt9v125_ds rev.. w 6/15 en 62 ?semiconductor components industries, llc,2015. appendix bCsensor core characteristics description of measurement conditions note: all measurements are done at nominal power supply voltages, at default settings, and at ambient room temperature except where noted. for microlens shifted array, mea- surements are performed in the window 32 32 pixels in the center of pixel array, where the signal value is maximum. all measurements in the dark are performed across the whole pixel array. measurement conditions 1 a standard pattern box (luminance 706 cd/m 2 , color temperature of 3100k halogen source) is used as an illumination source. a lens with f5.6 and a standard cm500 ir-cut filter (t = 1mm) is used to project the image from a uniformly illuminated surface of the pattern box to the sensor. signals in the center of each color plane, as an average of 128 frames, at default integration time and unity gain. values of dark signals, (see ?measure- ment conditions 6? on page 64) are subtracted from light signals. green response and response comparison are calculated according to the following formula: v g =(v gr + v gb )/2 (eq 21) s g =v g (lsb) (eq 22) r r =v r /v g (eq 23) r b =v b /v g (eq 24) measurement conditions 2 illumination source and lens-filter are the same as in ?measurement conditions 1?. image sensor characteristics are calculated for green pixels only, in a 16 x16 pixels windows for gr and gb color planes, in lsb on the sensor output. saturation signal is measured at exposure 10 times higher than exposure corresponding to 500 lsb on the sensor output at unity gain: v sat = (v grsat + v gbsat )/2 (eq 25) table 27: mt9v125 rev4 imager sensor core characteristics symbol parameter unit typ (average) measurement condition remarks sg green response lsb 516 conditions 1 t int = 1/120 s rr response comparison 0.611 conditions 1 t int = 1/120 s rb 0.539 conditions 1 t int = 1/120 s vsat pixel saturation signal lsb 1023 conditions 2 gain = 1 ? t readout noise lsb 4.11 conditions 3 gain = max ? t lsb 0.59 conditions 3 gain = 1 vdark dark current lsb/s 162 conditions 4 t s =55c, gain = max prnu photoresponse non-uniformity % 0.87 conditions 5 gain = 1 dsnu dark signal non-uniformit y % 0.045 conditions 6 gain = max snr signal-to-noise ratio db 38.5 conditions 5 gain = 1 dynr dynamic range db 71.7 conditions 6 gain = max
mt9v125_ds rev.. w 6/15 en 63 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix bCsensor core characteristics measurement conditions 3 the array is isolated from light. readout noise ? ? t ? is measured as average temporal noise across the whole pixel array, as an average for gr and gb color planes. readout noise is measured in lsb on the sensor output, using 128 frames, default integration time with two different setti ngs for gain: unity gain and maximum analog gain (511/32). measurement conditions 4 the array is isolated from light. dark cu rrent is measured at maximum analog gain (511/32), across the whole pixel array, in ls bs on the sensor output, at sensor tempera- ture equal to 55c. measurement conditions 5 illumination source and lens-filter are the same as in conditions 1. prnu (an average for gr and gb color planes) is calculated as a ratio of fixed pattern noise to the signal, for the signal equivalent to 50% of saturation (exposure time is adjusted), at unity gain, 16 by 16 pixels windows for gr and gb colo r planes, using 128 frames. values of dark signals (see conditions 6) are subtracted from light signals: prnu gr = (fpn gr /v gr ) x 100% (eq 26) prnu gb =(fpn gb /v gb ) x 100% (eq 27) prnu = (prnu gr +prnu gb )/2 (eq 28) snr (an average of gr and gb color planes) is calculated as a ratio of green signal to temporal noise at the signal equivalent to 50% of saturation (exposure time is adjusted), at unity gain, using 128 frames, 16 x 16 pixels windows for gr and gb color planes, according to the next formulas: snr gr =20 log 10 (v gr / ? tgr ) (eq 29) snr gb = 20 log 10 (vg / ? tgb ) (eq 30) snr = (snr gr + snr gb )/2 (eq 31) measurement conditions 6 the array is isolated from light. dark signal non-uniformity is measured across the whole pixel array at default settings except gain, which is set to the maximum analog value (511/32). dark signal non-uniformity (an average of gr and gb color planes) is calculated as a ratio of measured fixed pattern noise to the saturation signal (see ?measurement conditions 2? on page 63): dsnu gr = (32 * fpn gr / 511) / v grsat x 100% (eq 32) dsnu gb = (32 * fpn gb / 511) / v gbsat x 100% (eq 33) dsnu = (dsnu gr +dsnu gb )/2 (eq 34) dynamic range (an average of gr and gb color pl anes) is calculated as a ratio of the satu- ration signal (see ?measurement conditions 2? on page 63) to readout noise measured at the maximum analog gain value (511/32) (see ?measurement conditions 3?), according to next formulas: dynr gr =20 log 10 ((v grsat / ? tgr ) x (511/32)) (eq 35) dynr gb =20 log 10 ((v gbsat / ? tgb ) x (511/32)) (eq 36) dynr = (dynr gr +dynr gb )/2 (eq 37)
mt9v125_ds rev.. w 6/15 en 64 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix bCsensor core characteristics supplementary plots figure 47: typical signal to nois e ratio as a func tion of exposure measurement conditions the array is illuminated from davidson optronic tvo system using green spectral filter with ? max = 5505nm and full width half maximum (fwhm) = 40nm. during measure- ments, gain was adjusted to optimal for each value of exposure. signal to noise ratio vs exposure 0 10 20 30 40 50 0.0001 0.001 0.01 0.1 1 exposure, lux-s signal to noise ratio, db snr max readout noise limitation shot noise limitation
mt9v125_ds rev.. w 6/15 en 65 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor appendix bCsensor core characteristics figure 48: typical spectral characteristic mt9v125 r ev4 quantum efficiency 0 10 20 30 40 50 60 350 450 550 650 750 850 950 1050 wavelength (nm) quantum efficiency (%) blue green red
mt9v125: soc vga digital image sensor revision history mt9v125_ds rev.. w 6/15 en 67 ?semiconductor components industries, llc,2015. revision history rev. w. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/19/15 ? updated ?ordering information? on page 2 rev. v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/16/15 ? updated ?ordering information? on page 2 rev. u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/31/15 ? converted to on semiconductor template. rev. t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/11 ? updated trademarks ? applied updated template rev. s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/2/10 ? updated to non-confidential rev. r, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/6/10 ? updated to aptina template ? transfered registers to register reference rev. q, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/3/08 ? updated figure 2: ?typical usage conf iguration with overlay,? on page 7, moved labels closed to their respective buses ? added figure 11 and figure 12 on page 18 to explain awb measurement area ? updated description of awb window boundaries in table 15, ?camera control register?address page 2,? on page 63 ? updated figure 29 and table 13 on page 43 ? added figure 30 and table 14 on page 44 ? updated figure 3 on page 8 ? updated note 1 in table 13, ?parallel input data timing values using din_clk,? on page 43 rev. p, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/3/07 ?added ?appendix b?sensor core characteristics? on page 63. ? added figure 47: ?typical signal to noise ratio as a function of exposure,? on page 65. ? added figure 48: ?typical spectral characteristic,? on page 66. ? updated table 23, ?digital i/o parameters,? on page 54. ? updated figure 40 and figure 41 on page 61. ? updated figure 45 on page 62. rev. n, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/03/07 ? updated figure 32 on page 49, figure 33 on page 50, table 3 on page 9, table 21 on page 52 and, table 22 on page 53. rev. m, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/13/07 ? added i/o circuitry diagrams see figure 32 on page 49 and figure 33 on page 50. ? re-ordered pads for d in [7:0] and d out [7:0] in table 3 on page 9. ? updated figure 34 on page 51. ?fixed typos. ? added digitalclarity to trademarks on last page.
mt9v125_ds rev.. w 6/15 en 68 ?semiconductor components industries, llc,2015. mt9v125: soc vga digital image sensor revision history rev. l, production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/17/07 ? updates to table 1 on page 1, table 2 on page 2, and table 20 on page 51. ? updates to figure 3 on page 8, figure 15 on page 25, figure 19 on page 32. ? updates to figures 20 through figure 24 on page 37. ? updates to figure 34 on page 51. ? added figure 40 on page 61. ? minor changes for typos throughout document. rev. k, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/29/06 ? updates to figure 34 and table 19 on page 48. ? updates to table 23 and table 25 on page 55. rev. j, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/21/06 ? updated register/variable information in the following tables: table 10 on page 30, table 11 on page 32, table 12 on page 34, table 13 on page 39, table 14 on page 48, and table 15 on page 63 for rev4_3. ? added ordering information in table 2 on page 2. rev. h, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/6/06 ? changed colors in figure 1 on page 7, figure 2 on page 7, figure 3 on page 8, figure 5 on page 11, and figure 6 on page 11. rev. g, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/29/06 ? added ?data sheet applicable to? on page 1. ? added table 25, ?ntsc signal parameters,? on page 55. ? updated see ?sensor registers?short descriptions? on page 30. ? updated register information in table 13 on page 39, table 14 on page 48, and tabl e 15 on pag e 63 . ? updated package drawing figure 35: 52-b all ibga package outline drawing on page 56. rev. f, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/1/06 ? updated all figures that were not usin g marcom standard colors. no technical content of the figures was changed. ? updated equation 1 on page 28 through equation 20 on page 31 using framemaker equation tool. ? many changes were made to make the docu ment more consistent with marcom stan- dards. ?latin abbreviations were removed. ? ntsc/pal changed to ?ntsc and pal? or ?ntsc or pal? where appropriate. rev. e, production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/28/06 ? updated table 13 on page 43. ? updated figure 33 on page 50. ? updated figure 3 on page 8 and added note about v aa and vaapix. ? added note about v aa and vaapix to table 3 on page 9. ? fixed notes in table 4, readout mode register settings ? dout not qualified and table 6, readout mode register settings ? dout qualified. ? removed ?preliminary? designation on fi gure 20 on page 34, figure 21 on page 35, figure 23 on page 37, and figure 24 on page 37. ? updated figure 19 on page 32.
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v125: soc vga digital image sensor revision history mt9v125_ds rev.. w 6/15 en 69 ?semiconductor components industries, llc,2015 . rev. d, preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/06/06 ? updated figure 22 on page 36. rev. c, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/3/05 ? updated register definitions from rev1 to rev2. new register listing formation. ? updated ntsc/pal termination recomme ndations with smtpe compliant sche- matics. ? updated "minimum horizontal blanking (i n sensor stand-alone mode)" on page 29. ? updated "maximum shutter delay" on page 31. rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/29/05 ?updated to advance ? added register summaries; updated notation. ? added register descriptions; updated notation. ? added multiple chapters and art. rev a, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/05 ?initial release

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